1. Field of the Invention
The present invention relates to a solid-state image sensor.
2. Description of the Related Art
FIG. 1A is a plan view showing the plan layout of a solid-state image sensor. The solid-state image sensor shown in FIG. 1A includes an effective pixel region 1, optical black region 2, and peripheral circuit region 3. Each of the effective pixel region 1 and optical black region 2 includes a two-dimensional array of a plurality of pixels. An operational amplifier circuit, horizontal scanning circuit, and vertical scanning circuit, for example, are arranged in the peripheral circuit region 3. A light-shielding film made of a metal film opens in each pixel in the effective pixel region 1, while it covers almost the entire surfaces of the optical black region 2 and peripheral circuit region 3. A pixel signal from the optical black region 2 is used as a black-level reference signal. A planarizing film made of an insulating film such as a silicon oxide film is arranged on the light-shielding film for planarization. In this case, the planarizing film must have a given uniformity in order to suppress a color variation due to nonuniformity of the optical path difference between the pixels within the effective pixel region 1.
This planarizing film is formed by polishing and planarizing the surface of an insulating film such as a silicon oxide film deposited on a light-shielding film having steps using a CMP (Chemical Mechanical Polishing) method. The polishing rate of a silicon oxide film by CMP is slower on a light-shielding film with a high area occupancy than on a light-shielding film with a low area occupancy. Therefore, steps are generated on the surface of the planarizing film at the boundary between the effective pixel region in which the light-shielding film has a low area occupancy and the effective pixel region peripheral portion in which the light-shielding film has a high area occupancy. Due to factors associated with these steps, the thickness of the planarizing film varies between the central portion and outer peripheral portion of the effective pixel region, thus generating a color variation resulting from an optical path difference. Japanese patent Laid-Open No. 2001-196571 discloses a method for solving the above-mentioned problem. According to Japanese Patent Laid-Open No. 2001-196571, the steps on the planarizing film at the boundary between the effective pixel region and the effective pixel region peripheral portion can be reduced by arranging, in a groove formed in advance, the light-shielding film in the effective pixel region peripheral portion, which has a high area occupancy.
Unfortunately, the method described in Japanese Patent Laid-Open No. 2001-196571 is disadvantageous in that it requires a new process of forming a groove. Also, this method is insufficient to fundamentally eliminate the nonuniformity of the planarizing film due to the difference in area occupancy of the light-shielding film.